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CXP878P60
CMOS 8-bit Single Chip Microcomputer
Description The CXP878P60 is a CMOS 8-bit microcomputer which consists of A/D converter, serial interface, timer/counter, time base timer, high precision timing pattern generation circuit, PWM output, VISS/VASS circuit, 32kHz timer/counter, remote control reception circuit, HSYNC counter, VSYNC separator and the measurement circuit which measures signals of capstan FG and drum FG/PG and other servo systems, as well as basic configurations like 8-bit CPU, PROM, RAM and I/O port. They are integrated into a single chip. Also the CXP878P60 provides sleep/stop functions which enable to lower power consumption. The CXP878P60 is the PROM-incorporated version of the CXP87860 with built-in mask ROM. This provides the additional feature of being able to write directly into the program. Thus, it is most suitable for evaluation use during system developement and for small-quantity production. 100 pin QFP (PIastic)
Structure Silicon gate CMOS IC
Features * A wide instruction set (213 instructions) which covers various types of data -- 16-bit arithmetic/multiplication and division/Boolean bit operation instructions * Minimum instruction cycle 250ns at 16MHz operation (4.5V to 5.5V) 122s at 32kHz operation * Incorporated PROM capacity 60K bytes * Incorporated RAM capacity 2048 bytes * Peripheral functions -- A/D converter 8 bits, 12 channels, successive approximation system (Conversion time of 20.0s at 16MHz) -- Serial interface Incorporated buffer RAM (Auto transfer for 1 to 32 bytes), 1 channel Incorporated 8-bit and 8-stage FIFO (Auto transfer for 1 to 8 bytes), 1 channel Incorporated two-wire 8-bit and 8-stage FIFO (Auto transfer for 1 to 8 bytes), 1 channel -- Timer 8-bit timer, 8-bit timer/counter, 19-bit time base timer, 32kHz timer/counter -- High precision timing pattern generator PPG: maximum of 19 pins, 32 stages programmable RTG: 5 pins, 2 channels -- PWM/DA gate output PWM: 12 bits, 2 channels (Repetitive frequency of 62kHz at 16MHz) DA gate pulse output: 13 bits, 4 channels -- Servo input control Capstan FG, drum FG/PG, CTL input -- VSYNC separator -- FRC capture unit Incorporated 26-bit and 8-stage FIFO -- PWM output 14 bits -- VISS/VASS circuit Pulse duty auto detection circuit -- Remote control reception circuit 8-bit pulse measurement counter with on-chip, 6-stage FIFO -- HSYNC counter 12-bit event counter (Counts SYNC1 input.) * Interruption 23 factors, 15 vectors, multi-interruption possible * Standby mode Sleep/stop * Package 100-pin plastic QFP
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
-1-
E96214-PS
Block Diagram
AVss INT0 INT1/NMI INT2 TEX TX EXTAL XTAL RST MP VDD Vss Vpp
AVDD
AVREF
2 2 8 PA0 to PA7 SPC700 CPU CORE
PORT B PORT A
AN0 to AN11 CLOCK GENERATOR/ SYSTEM CONTROL 8 PB0 to PB7
12
A/D CONVERTER
SCL0 SCL1 SDA0 SDA1 FIFO
SERIAL INTERFACE UNIT (CH2)
SI1 SO1 SCK1 FIFO 8 2 2 6 4 4
INTERRUPT CONTROLLER
CS0 SI0 SO0 SCK0 PROM 60K BYTES RAM 2048 BYTES
PORT D PORT C
SERIAL INTERFACE UNIT (CH0) RAM 8
PC0 to PC7
SERIAL INTERFACE UNIT (CH1)
PD0 to PD7
EC
8 BIT TIMER/COUNTER 0
PE0 to PE1 PE2 to PE7 PF0 to PF3 PF4 to PF7
EXI0 EXI1 2 2 FRC CAPTURE UNIT FIFO
DRUM 3 FIFO 2
SERVO INPUT CONTROL
32kHz TIMER/COUNTER
CFG DFG DPG PBCTL
CTL
PORT G
RMC
REMOCON INPUT
PWM RAM
14 BIT PWM GENERATOR
PROGRAMMABLE PATTERN GENERATOR 2
REALTIME PULSE GENERATOR CH0 CH1
PORT I
VISS/VASS
PORT H
12 BIT PWM GENERATOR CH0
12 BIT PWM GENERATOR CH1 4
PWM0 DAA0 DAB0 PWM1 DAA1 DAB1
HSYNC COUNTER
HCOUT
19
5
ADJ
CKOUT
PPO0 to PPO18
RTO3 to RTO7
PORT J
-2-
CAPSTAN
PORT F
SYNC0 SYNC1 2 PRESCALER/ TIME BASE TIMER
VSYNC SEPARATOR
PORT E
TO/DDO
8 BIT TIMER 1
8
PG0 to PG7
8
PH0 to PH7
7
PI1 to PI7
8
PJ0 to PJ7
CXP878P60
CXP878P60
Pin Assignment (Top View)
PI3/TO/DDO/ADJ
PB6/PPO14
PB7/PPO15
PA0/PPO0
PA1/PPO1
PA2/PPO2
PA3/PPO3
PA4/PPO4
PA5/PPO5
PA6/PPO6
PA7/PPO7
PI4/INT1/NMI
Vpp
VDD
VSS
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 PB5/PPO13 PB4/PPO12 PB3/PPO11 PB2/PPO10 PB1/PPO9 PB0/PPO8 PC7/RTO7 PC6/RTO6 PC5/RTO5 PC4/RTO4 PC3/RTO3 PC2/PPO18 PC1/PPO17 PC0/PPO16 PJ7 PJ6 PJ5 PJ4 PJ3 PJ2 PJ1 PJ0 PD7 PD6 PD5 PD4 PD3/SDA1 PD2/SDA0 PD1/SCL1 PD0/SCL0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 PI6/SO1 PI7/SI1 PE0/INT0/CKOUT PE1/EC/INT2/HCOUT PE2/PWM0 PE3/PWM1 PE4/DAA0 PE5/DAA1 PE6/DAB0 PE7/DAB1 PG0/CFG PG1/DFG PG2/DPG PG3/PBCTL PG4/SYNC0 PG5/SYNC1 PG6/EXI0 PG7/EXI1 AN0 AN1 AN2 AN3 PF0/AN4 PF1/AN5 PF2/AN6 PF3/AN7 AVDD AVREF AVSS PF4/AN8
TX
TEX
PI1/RMC
PI2/PWM
Note) 1. Vpp (Pin 90) is always connected to VDD. 2. Vss (Pins 41 and 88) are both connected to GND. 3. MP (Pin 39) is always connected to GND.
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PF7/AN11
PF6/AN10
PF5/AN9
EXTAL
SCK0
XTAL
RST
SO0
PH7
PH6
PH5
PH4
PH3
PH2
PH1
PH0
CS0
VSS
MP
SI0
PI5/SCK1
CXP878P60
Pin Description Symbol PA0/PPO0 to PA7/PPO7 I/O Output/ Real-time output (Port A) 8-bit output port. Data is gated with PPO contents by OR-gate and they are output. (8 pins) (Port B) 8-bit output port. Data is gated with PPO contents by OR-gate and they are output. (8 pins) (Port C) 8-bit I/O port. I/O can be set in a unit of single bits. Data is gated with PPO or RTO contents by OR-gate and they are output. (8 pins) Description
PB0/PPO8 to PB7/PPO15 PC0/PPO16 to PC2/PPO18 PC3/RTO3 to PC7/RTO7 PD0/SCL0 PD1/SCL1 PD2/SDA0 PD3/SDA1 PD4 to PD7 PE0/INT0/ CKOUT PE1/EC/INT2/ HCOUT PE2/PWM0 PE3/PWM1 PE4/DAA0 PE5/DAA1 PE6/DAB0 PE7/DAB1 AN0 to AN3 PF0/AN4 to PF3/AN7 PF4/AN8 to PF7/AN11 SCK0 SO0 SI0 CS0
Output/ Real-time output I/O/ Real-time output I/O/ Real-time output
Programmable pattern generator (PPG) output. Functions as high precision real-time pulse output port. PB0 and PB2 can be 3-state controlled with PPG. (19 pins)
Real-time pulse generator (RTG) output. Functions as high precision real-time pulse output port. PC3 can be 3-state controlled with RTG. (5 pins) Serial clock (CH2) I/O. (2 pins) Serial data (CH2) I/O. (2 pins)
I/O
(Port D) 8-bit I/O port. I/O can be set in a unit of single bits for upper 4 bits. Can drive 12mA sink current. Lower 4-bit output is N-ch open drain. (8 pins)
Input/Input/Output
Input to request external interruption. Active at the falling edge. (Port E) 8-bit port. Lower 2 bits are for inputs; upper 6 bits are for outputs. (8 pins) External event input for timer/counter. PWM outputs. (2 pins)
System clock frequency dividing output.
Input/Input/Input/ Output Output/Output Output/Output Output/Output Output/Output Output/Output Output/Output Input Input/Input
Input to request external Coinsidence signal output of interruption. Active at the falling edge. HSYNC counter.
DA gate pulse outputs. (4 pins)
Analog input to A/D converter. (12 pins) (Port F) 8-bit port. Lower 4 bits are for inputs; upper 4 bits are for outputs. Lower 4 bits also serve as standby release input pin. (8 pins) Serial clock (CH0) I/O. Serial data (CH0) output. Serial data (CH0) input. Serial chip select (CH0) input. -4-
Output/Input I/O Ouput Input Input
CXP878P60
Symbol PG0/CFG PG1/DFG PG2/DPG PG3/PBCTL PG4/SYNC0 PG5/SYNC1 PG6/EXI0 PG7/EXI1
I/O Input/Input Input/Input Input/Input Input/Input Input/Input Input/Input Input/Input Input/Input (Port G) 8-bit input port. (8 pins)
Description Capstan FG input. Drum FG input. Drum PG input. Playback CTL pulse input. External event input for timer/counter. Composite sync signal input. (2 pins) External input to FRC capture unit. (2 pins) (Port H) 8-bit output port ; N-ch open drain output of medium drive voltage (12V) and large current (12mA). (8 pins) Remote control reception circuit input. 14-bit PWM output. (Port I) 7-bit I/O port. I/O port can be set in a unit of single bits. (7 pins) Timer/counter, CTL duty detection, 32kHz oscillation adjustment output. Input to request external interruption and non-maskable interruption. Active at the falling edge. Serial clock (CH1) I/O. Serial data (CH1) output. Serial data (CH1) input. (Port J) 8-bit I/O port. I/O and standby release input function can be set in a unit of single bits. Connects a crystal oscillator for system clock. When supplying the external clock, input the external clock to EXTAL and input the opposite phase clock to XTAL. Connects a crystal oscillator for 32kHz timer/counter clock. The 32kHz crystal oscillator is inserted between TEX and TX. When used as event counter, connect the clock source to TEX and leave TX open. System reset; active at Low level. Test mode input. Always connect to GND. Positive power supply of A/D converter.
PH0 to PH7
Output
PI1/RMC PI2/PWM PI3/TO/ DDO/ADJ PI4/INT1/ NMI PI5/SCK1 PI6/SO1 PI7/SI1 PJ0 to PJ7 EXTAL XTAL TEX TX RST MP AVDD AVREF AVss VDD Vpp Vss
I/O/Input I/O/Output I/O/Output/ Output/Output I/O/Input/Input I/O/I/O I/O/Output I/O/Input I/O Input Output Input Output Input Input
Input
Reference voltage input of A/D converter. GND of A/D converter. Positive power supply. Connect VDD pin to VDD. Positive power supply for incorporated PROM writing. In normal operation, connect to VDD. GND. Connect both Vss pins to GND.
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CXP878P60
Input/Output Circuit Formats for Pins Pin Port A Port B PA0 /PPO0 to PA7/PPO7 PB4/PPO12 to PB7/PPO15
PPO data
Circuit format
When reset
Port A, Port B data
Hi-Z
Data bus RD (Port A or Port B)
Output becomes active from high impedance by data writing to port register.
12 pins
PB0 /PPO8 PB2/PPO10
PPO8, PPO10 data
Hi-Z
PB0, PB2 data
Data bus RD (Port B)
2 pins
PPO9, PPO11 data PPG control status register bit 0 3-state control selection PPO9, PPO11 data Output becomes active from high impedance by data writing to port register.
PB1/PPO9 PB3/PPO11
PB1, PB3 data
Hi-Z
Data bus RD (Port B) Output becomes active from high impedance by data writing to port register.
2 pins
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CXP878P60
Pin Port C
Circuit format
When reset
PC0/PPO16 to PC2/PPO18 PC5/RTO5 to PC7/RTO7
Data bus
PPO, RTO data Port C data IP Input protection circuit
Hi-Z
Port C direction "0" when reset
6 pins
RD (Port C)
RTO3 data PC3 data
PC3/RTO3
PC3 direction "0" when reset IP Data bus RD (Port C) RTO4 data
Hi-Z
1 pin
RTG interruption control register bit 7 3-state control selection
RTO4 data PC4 data
PC4/RTO4
PC4 direction "0" when reset Data bus RD (Port C) RTO data is OR-gate data of CH0 and CH1. IP
Hi-Z
1 pin
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CXP878P60
Pin Port D
Circuit format
When reset
SCL, SDA Serial interface CH2 output enable
PD0/SCL0 PD1/SCL1 PD2/SDA0 PD3/SDA1
Port D data IP RD (Port D) SCL, SDA (Serial CH2 circuit) Schmitt input
Data bus
Hi-Z
BUS SW To another serial CH2 pin Large current 12mA
4 pins Port D
PD4 to PD7
Port D data
Port D direction "0" when reset Data bus
IP
Hi-Z
4 pins Port E
RD (Port D)
Large current 12mA
ESL0 Port E selection ESL1 PS1 PS2 PS3 01 10 MPX 11
PE0/INT0/ CKOUT
Hi-Z
IP
Data bus RD (Port E)
1 pin
Interruption circuit
-8-
CXP878P60
Pin Port E
From HSYNC counter Hi-Z control HCOUT
Circuit format
When reset
PE1/EC/INT2 /HCOUT
IP
Hi-Z
Data bus RD (Port E) Interruption circuit/ event counter
1 pin
Port E
DA gate output, PWM output
PE2/PWM0 PE3/PWM1 PE4/DAA0 PE5/DAA1
Hi-Z control Port E data
MPX
Hi-Z
Port/DA output selection "0" when reset Data bus
4 pins
RD (Port E)
Port E
DA gate output Hi-Z control MPX
PE6/DAB0 PE7/DAB1
Port E data
High level
Port/DA output selection "1" when reset Data bus
2 pins
RD (Port E)
AN0 to AN3 4 pins
Input multiplexer IP A/D converter
Hi-Z
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CXP878P60
Pin Port F PF0/AN4 to PF3/AN7
Circuit format
Input multiplexer IP A/D converter
When reset
Hi-Z
Data bus
4 pins Port F
Port F data
RD (Port F)
PF4/AN8 to PF7/AN11
Data bus RD (Port F) Port A/D selection "0" when reset
IP
Hi-Z
A/D converter Input multiplexer
4 pins Port G PG0/CFG PG1/DFG PG2/DPG PG3/PBCTL PG4/SYNC0 PG5/SYNC1 PG6/EXI0 PG7/EXI1 8 pins Port H
Schmitt input IP
Servo input Data bus RD (Port G)
Hi-Z
Note) For PG4 and PG5 input format, there is TTL Schmitt input with product.
PH0 to PH7
Port H data
Hi-Z
Data bus RD (Port H) Large current 12mA Medium drive voltage 12V
8 pins
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CXP878P60
Pin Port I
Circuit format
Port I function selection "0" when reset PI2...14-bit PWM PI3...Timer/counter, CTL duty detection circuit, 32kHz timer Port I data Port I direction "0" when reset Data bus RD (Port I)
When reset
PI2/PWM PI3/TO/ DDO/ADJ
MPX
Hi-Z
IP
2 pins
Port I
Port I data
PI1/RMC PI4/INT1/NMI PI7/SI1
Data bus
Port I direction "0" when reset IP
Hi-Z
RD (Port I)
3 pins Port I
PI1...Remote control circuit PI4...Interruption circuit PI7...Serial interface CH1
Schmitt input
Port I function selection Serial interface CH1 Port I data Port I direction "0" when reset Data bus RD (PortI) MPX
PI5/SCK1 PI6/SO1
MPX
Hi-Z
IP
2 pins Port J
Serial interface CH1
PI6 is not Schmitt input.
Port J data
Port J direction
PJ0 to PJ7
Data bus
"0" when reset IP RD (Port J) Standby release Data bus
Hi-Z
Edge detection
8 pins
RD (Port J direction)
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CXP878P60
Pin CS0 SI0 2 pins
Circuit format
Schmitt input IP CS Serial interface CH0 SI
When reset
Hi-Z
SO0
SO Serial interface CH0
Hi-Z
1 pin
SO0 output enable
SCK0
SCK Serial interface CH0 SCK0 output enable SCK IP
Hi-Z
1 pin
Schmitt input
EXTAL XTAL
EXTAL
IP
* Shows the circuit composition during oscillation. * Feedback resistor is removed during stop mode.
Oscillation
2 pins
XTAL
TEX TX
32kHz timer/counter TEX IP
2 pins
TX
* Shows the circuit composition during oscillation. * Feedback resistor is removed during 32kHz oscillation circuit stop by software. At this time TEX pin outputs Low level and TX pin outputs High level.
Oscillation
Pull-up resistor
RST
Schmitt input
Low level
IP
1 pin
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CXP878P60
Absolute Maximum Ratings Item Symbol VDD Vpp Supply voltage AVDD AVSS Input voltage Output voltage VIN VOUT Rating -0.3 to +7.0 -0.3 to +13 AVss to +7.01 -0.3 to +0.3 -0.3 to +7.02 -0.3 to +7.02 -0.3 to +15.0 -5 -50 15 20 130 -10 to +75 -55 to +150 600 Unit V V V V V V V mA mA mA mA mA C C mW QFP Total of output pins Port H pin Incorporated PROM
(Vss = 0V reference) Remarks
Medium drive output voltage VOUTP High level output current IOH High level total output current IOH Low level output current IOL IOLC Low level total output current IOL Operating temperature Storage temperature Allowable power dissipation Topr Tstg PD
Ports excluding large current output (value per pin) Large current output port (value per pin3) Total of output pins
1 AVDD should not exceed VDD + 0.3V. 2 VIN and VOUT should not exceed VDD + 0.3V. 3 The large current drive transistors are the N-CH transistors of the Port D (PD) and Port H (PH). Note) Usage exceeding absolute maximum ratings may permanently impair the LSI. Normal operation should be conducted under the recommended operating conditions. Exceeding those conditions may adversely affect the reliability of the LSI.
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CXP878P60
Recommended Operating Conditions Item Symbol Min. 4.5 3.5 2.7 2.0 Analog supply voltage AVDD VIH High level input voltage VIHS VIHTS VIHEX VIL Low level input voltage VILS VILTS VILEX Operating temperature Topr 1 2 3 4 5 6 7 4.5 0.7VDD 0.8VDD 2.2 Max. 5.5 5.5 5.5 5.5 5.5 VDD VDD 5.5 5.5 Unit V V V V V V V V V V V V V V C
(Vss = 0V reference) Remarks Guaranteed operation range for 1/2 and 1/4 frequency dividing modes Guaranteed operation range for 1/16 frequency dividing mode or during sleep mode Guaranteed operation range by TEX clock Guaranteed data hold range during stop mode 1 Includes the serial CH2 input2 CMOS Schmitt input3 and PE0/INT0 pin CMOS Schmitt input7 TTL Schmitt input4 EXTAL pin5 and TEX pin6 Includes the serial CH2 input2 CMOS Schmitt input3 and PE0/INT0 pin TTL Schmitt input4 EXTAL pin5 and TEX pin6
Supply voltage
VDD
VDD - 0.4 VDD + 0.3 0 0 0 -0.3 -10 0.3VDD 0.2VDD 0.8 0.4 +75
AVDD and VDD should be set to the same voltage. Normal input port (PC, PD4 to PD7, PF0 to PF3, PG, PI and PJ), MP pin SCK0, RST, EC/INT2, RMC, INT1/NMI, SCK1 and SI1 PG4 and PG5 (When TTL Schmitt input is selected for the product) Specifies only when the external clock is input. Specifies only when the external event count clock is input. CS0, SI0, and PG (For PG4 and PG5, when CMOS Schmitt input is selected for the product.)
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CXP878P60
Electrical Characteristics DC Characteristics (VDD = 4.5 to 5.5V) Item High level output voltage Symbol VOH Pins PA to PC, PD4 to PD7, PE2 to PE7, PF4 to PF7, PH (VOL only) PI1 to PI7 PJ, SO0, SCK0 PD, PH PD0 to PD3 (SCL0, SCL1 SDA0, SDA1) IIHE IILE Input current IIHT IILT IILR TEX RST PA to PG, PI, PJ, MP AN0 to AN3, CS0, SI0, SO0 SCK0 PH PD0 to PD3 EXTAL Conditions VDD = 4.5V, IOH = -0.5mA VDD = 4.5V, IOH = -1.2mA VDD = 4.5V, IOL = 1.8mA VDD = 4.5V, IOL = 3.6mA VDD = 4.5V, IOL = 12.0mA VDD = 4.5V, IOL = 3.0mA VDD = 4.5V, IOL = 6.0mA VDD = 5.5V, VIH = 5.5V VDD = 5.5V, VIL = 0.4V VDD = 5.5V, VIH = 5.5V VDD = 5.5V, VIL = 0.4V 0.5 -0.5 0.1 -0.1 -1.5 (Ta = -10 to +75C, Vss = 0V reference) Min. 4.0 3.5 0.4 0.6 1.5 0.4 0.6 40 -40 10 -10 -400 Typ. Max. Unit V V V V V V V A A A A A
Low level output voltage
VOL
I/O leakage current
IIZ
VDD = 5.5V, VI = 0, 5.5V
10
A
Open drain output leakage ILOH current (in N-CH Tr off state) Serial interface CH2 bus switch connection impedance (in output Tr off state)
VDD = 5.5V, VOH = 12V VDD = 5.5V, VOH = 5.5V
50 10
A A
RBS
SCL0: SCL1 SDA0: SDA1
VDD = 4.5V VSCL0 = VSCL1 = 2.25V VSDA0 = VSDA1 = 2.25V
120
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CXP878P60
Item
Symbol IDD1
Pins
Conditions High-speed mode (1/2 frequency dividing clock) operation VDD = 5V 0.5V
Min.
Typ. 31
Max. 50
Unit mA
IDDS1 Supply current1 VDD
Sleep mode VDD = 5V 0.5V
2.3
8
mA
IDD2
32kHz crystal oscillation (C1 = C2 = 47pF) VDD = 3V 0.3V 44 110 A
IDDS2
Sleep mode VDD = 3V 0.3V
9
35
A
IDDS3
PC, PD, PE0, PE1, PF, PG, PI1 to PI7 PJ, CS0, SI0, SCK0, AN0 to AN3, EXTAL, XTAL, TEX, TX, MP, RST
Stop mode (EXTAL and TEX pins oscillation stop) VDD = 5V 0.5V
30
A
Input capacity
CIN
Clock 1MHz 0V other than the measured pins
10
20
pF
1 When all output pins are open.
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CXP878P60
AC Characteristics (1) Clock timing Item System clock frequency System clock input pulse width System clock input rise and fall times Event count clock input pulse width Event count clock input rise and fall times System clock frequency Event count clock input pulse width Event count clock input rise and fall times 1 Symbol fC Pins XTAL EXTAL XTAL EXTAL XTAL EXTAL EC EC TEX TX TEX TEX
(Ta = -10 to +75C, VDD = 4.5 to 5.5V, Vss = 0V reference) Conditions Fig. 1, Fig. 2 Fig. 1, Fig. 2 (External clock drive) Fig. 1, Fig. 2 (External clock drive) Fig. 3 Fig. 3 Fig. 2 VDD = 2.7 to 5.5V (32kHz clock applied condition) Fig. 3 Fig. 3 10 20 32.768 4tsys1 20 Min. 1 28 200 Typ. Max. 16 Unit MHz ns ns ns ns kHz s ms
tXL, tXH tCR, tCF tEH, tEL tER, tEF
fC
tTL, tTH tTR, tTF
tsys indicates three values according to the contents of the clock control register (CLC; 00FEH) upper 2 bits
(CPU clock selection). tsys [ns] = 2000/fc (Upper 2 bits = "00"), 4000/fc (Upper 2 bits = "01"), 16000/fc (Upper 2 bits = "11")
Fig. 1. Clock timing
1/fc
VDD - 0.4V EXTAL 0.4V tXH tCF tXL tCR
Fig. 2. Clock applied condition
Crystal oscillation Ceramic oscillation External clock 32kHz clock applied condition crystal oscillation
EXTAL C1
XTAL C2
EXTAL
XTAL C1
TEX
TX C2
74HC04
Fig. 3. Event count clock timing
0.8VDD 0.2VDD tEH tTH tEF tTF tEL tTL tER tTR
TEX EC
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CXP878P60
(2) Serial transfer (CH0) Item CS SCK delay time CS SCK floating delay time CS SO delay time CS SO floating delay time CS High level width SCK cycle time SCK High and Low level widths SI input setup time (for SCK ) SI input hold time (for SCK ) SCK SO delay time Note 1) Symbol Pin SCK0
(Ta = -10 to +75C, VDD = 4.5 to 5.5V, Vss = 0V reference) Condition Chip select transfer mode (SCK = output mode) Chip select transfer mode (SCK = output mode) Chip select transfer mode Chip select transfer mode Chip select transfer mode Input mode SCK0 Output mode Input mode SCK0 Output mode SCK input mode SI0 SCK output mode SCK input mode SI0 SCK output mode SCK input mode SO0 SCK output mode Min. Max. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns 2tsys + 200 100 ns ns
tDCSK
tsys + 200 tsys + 200 tsys + 200 tsys + 200 tsys + 200
2tsys + 200 16000/fc
tDCSKF SCK0 tDCSO
SO0
tDCSOF SO0 tWHCS CS0 tKCY tKH tKL tSIK tKSI tKSO
tsys + 100
8000/fc - 100 -tsys + 100 200 2tsys + 100 100
tsys indicates three values according to the contents of the clock control register (CLC: 00FEH) upper
2 bits (CPU clock selection). tsys [ns] = 2000/fc (Upper 2 bits = "00"), 4000/fc (Upper 2 bits = "01"), 16000/fc (Upper 2 bits = "11") Note 2) The load of SCK output mode and SO output delay time is 50pF + 1TTL.
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CXP878P60
Fig. 4. Serial transfer timing (CH0)
tWHCS
CS0
0.8VDD
0.2VDD
tKCY tDCSK tKL tKH tDCSKF
0.8VDD SCK0 0.2VDD
0.8VDD
tSIK
tKSI
0.8VDD SI0 Input data 0.2VDD
tDCSO
tKSO
tDCSOF
0.8VDD SO0 Output data 0.2VDD
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CXP878P60
Serial transfer (CH1) (SIO mode) Item SCK1 cycle time SCK1 High and Low level widths SI1 input setup time (for SCK1 ) SI1 input hold time (for SCK1 ) SCK1 SO1 delay time Note 1) Symbol Pin SCK1
(Ta = -10 to +75C, VDD = 4.5 to 5.5V, Vss = 0V reference) Condition Input mode Output mode Input mode SCK1 Output mode SCK1 input mode SI1 SCK1 output mode SCK1 input mode SI1 SCK1 output mode SCK1 input mode SO1 SCK1 output mode Min. 2tsys + 200 16000/fc Max. Unit ns ns ns ns ns ns ns ns
tKCY tKH tKL tSIK tKSI tKSO
tsys + 100
8000/fc - 100 100 200
tsys + 200
100
tsys + 200
100
ns ns
tsys indicates three values according to the contents of the clock control register (CLC: 00FEH) upper
2 bits (CPU clock selection). tsys [ns] = 2000/fc (Upper 2 bits = "00"), 4000/fc (Upper 2 bits = "01"), 16000/fc (Upper 2 bits = "11") Note 2) The load of SCK1 output mode and SO1 output delay time is 50pF + 1TTL.
Fig. 5. Serial transfer CH1 timing (SIO mode)
tKCY tKL tKH
SCK1 0.8VDD 0.2VDD
tSIK
tKSI
0.8VDD SI1 Input data 0.2VDD
tKSO
0.8VDD SO1 0.2VDD Output data
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CXP878P60
Serial transfer (CH1) (Special mode) (Ta = -10 to +75C, VDD = 4.5 to 5.5V, Vss = 0V reference) Item SO1 cycle time SI1 data setup time SI1 data hold time 1 Symbol Pin SO1 SI1 SI1 SI1 1 2 2 Condition Min. Typ. 104 Max. Unit s s s
tLCY tLSU tLHD
tLCY is specified only when serial mode register (CH1) (SIOM1: 05FZH) lower 2 bits (SO1 clock selection)
has been set at 104s. Note) The load of SO1 pin is 50pF + 1TTL.
Fig. 6. Serial transfer CH1 timing (Special mode)
tLCY tLCY
SO1
Start bit
Output data bit
0.5VDD
tLCY/2 tLSU tLHD 0.8VDD 0.2VDD
SI1
Input data bit
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CXP878P60
Serial transfer (CH2) Item SCL clock frequency Bus-free time before starting transfer Hold time for starting transfer Clock Low level width Clock High level width Setup time for repeated transfers Data hold time Data setup time SDA, SCL rise time SDA, SCL fall time Setup time for transfer completion
(Ta = -10 to +75C, VDD = 4.5 to 5.5V, Vss = 0V reference) Symbol fSLC Pin SCL SDA, SCL SDA, SCL SCL SCL SDA, SCL SDA, SCL SDA, SCL SDA, SCL SDA, SCL SDA, SCL 1.6 2.6 1.0 1.0 1.0 1.0 01 100 300 300 Condition Min. Max. 400 Unit kHz s s s s s s ns ns ns s
tBUF tHD; STA tLOW tHIGH tSU; STA tHD; DAT tSU; DAT tR tF tSU; STO
1 The SCL fall time (300ns Max.) is not included in the data hold time.
Fig. 7. Serial transfer timing (CH2)
SDA tBUF tR tF tHD; STA
SCL tHD; STA tSU; STA P S tLOW tHD; DAT tHIGH tSU; DAT St tSU; STO P
Fig. 8. Device recommended circuit
Device
Device
RS SDA0 (or SDA1) SCL0 (or SCL1)
RS RS
RS RP
RP
* A pull-up resistor (RP) must be connected to SDA0 (or SDA1) and SCL0 (or SCL1). * The SDA0 (or SDA1) and SCL0 (or SCL1) series resistance (Rs = 300 or less) can be used to reduce the spike noise caused by CRT flashover.
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CXP878P60
(3) HSYNC counter Item External clock input frequency External clock input pulse width External clock input rise and fall times HCOUT output delay time (for SYNC1 ) HCOUT output rise and fall times Note1) Symbol fHCK
(Ta = -10 to +75C, VDD = 4.5 to 5.5V, Vss = 0V reference) Pin SYNC1 SYNC1 SYNC1 HCOUT HCOUT External clock input SYNC1 tR = tF = 6ns External clock input SYNC1 tR = tF = 6ns 33 200 Condition Min. Typ. Max. 12 Unit MHz ns ns
tWH, tWL tR, tF tHLH, tHHL tTLH tTHL
tsys + 220 ns
50 25 ns ns
tsys indicates three values according to the contents of the clock control register (CLC: 00FEH) upper
2 bits (CPU clock selection).
tsys [ns] = 2000/fc (Upper 2 bits = "00"), 4000/fc (Upper 2 bits = "01"), 16000/fc (Upper 2 bits = "11").
Note2) The load of HCOUT pin is 50pF.
Fig. 9. HSYNC counter timing
1/fHCK tWH tF 0.8VDD 0.5VDD 0.2VDD tWL tHLH 0.8VDD HCOUT 0.5VDD 0.2VDD tR
SYNC1
tHHL
tTLH
tTHL
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CXP878P60
(4) A/D converter characteristics (Ta = -10 to +75C, VDD = AVDD = 4.5 to 5.5V, AVREF = 4.0 to AVDD, Vss = AVSS = 0V reference) Item Resolution Linearity error Absolute error Conversion time Sampling time Ta = 25C VDD = AVDD = AVREF = 5.0V VSS = AVSS = 0V Symbol Pins Conditions Min. Typ. Max. 8 1 2 160/fADC1 12/fADC1 AVREF AN0 to AN11 Operating mode AVREF IREFS Sleep mode Stop mode 32kHz operating mode AVDD - 0.5 0 0.6 AVDD AVREF 1.0 10 Unit Bits LSB LSB s s V V mA A
tCONV tSAMP
VIAN IREF
Reference input voltage VREF Analog input voltage
AVREF current
Fig. 10. Definitions of A/D converter terms
FFH FEH
Digital conversion value
1 fADC indicates the below values due to the ADC operation clock selection (PCC: 05F8H) bit 3 and clock control register (CLC: 00FEH) upper 2 bits.
PCC bit 3 CLC upper 2 bits
0 (/2 selection) fADC = fC/2 fADC = fC/4 fADC = fC/16
1 ( selection) fADC = fC fADC = fC/2 fADC = fC/8
00 ( = fEX/2)
Linearity error
01 ( = fEX/4)
01H 00H Analog input
11 ( = fEX/16)
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CXP878P60
(5) Interruption, reset input Item
(Ta = -10 to +75C, VDD = 4.5 to 5.5V, Vss = 0V reference) Symbol Pins INT0 INT1 INT2 NMI PJ0 to PJ7 RST Conditions Min. Max. Unit
External interruption High and Low level widths
tIH tIL tRSL
1
s
Reset input Low level width
32/fc
s
Fig. 11. Interruption input timing
INT0 INT1 INT2 NMI PJ0 to PJ7 (During standby release input) (Falling edge)
tIH
tIL
0.8VDD 0.2VDD
Fig. 12. Reset input timing
tRSL
RST 0.2VDD
(6) Others Item CFG input High and Low level widths Symbol Pins CFG DFG DPG DPG PBCTL EXI0 EXI1
(Ta = -10 to +75C, VDD = 4.5 to 5.5V, Vss = 0V reference) Conditions Min. 24tFRC + 200 16tFRC + 200 8tFRC + 200 16tFRC + 200 Max. Unit ns ns ns ns ns ns
tCFH tCFL tDFH DFG input High and Low level widths tDFL DPG minimum pulse width tDPW
DPG minimum removal time PBCTL input High and Low level widths
trem
tCTH tCTL tEIH EXI input High and Low level widths tEIL
Note 1) Note 2)
tsys = 2000/fc tsys = 2000/fc
8tFRC + 200 + tsys 8tFRC + 200 + tsys
tFRC = 1000/fc [ns] tsys indicates three values according to the contents of the clock control register (CLC: 00FEH) upper 2 bits
(CPU clock selection). tsys [ns] = 2000/fc (Upper 2 bits = "00"), 4000/fc (Upper 2 bits = "01"), 16000/fc (Upper 2 bits = "11")
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CXP878P60
Fig. 13. Other timings
tCFH tCFL
0.8VDD CFG 0.2VDD
tDFH
tDFL
0.8VDD DFG 0.2VDD
tDPW trem
trem
0.8VDD DPG
tCTH
tCTL
0.8VDD PBCTL 0.2VDD
tEIH
tEIL
EXI0 EXI1
0.8VDD 0.2VDD
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CXP878P60
Supplement Fig. 14. Recommended oscillation circuit
(i) (ii)
EXTAL
XTAL Rd
TEX
TX Rd
C1
C2
C1
C2
Manufacturer
Model
fc (MHz) 8.00
C1 (pF) 10
C2 (pF) 10
Rd ()
Circuit example
RIVER ELETEC CO., LTD.
HC-49/U03
10.00 12.00 16.00 8.00 16 (12) 16 (12) 12 12 30 16 (12) 16 (12) 12 12 18 5 5
0
(i)
HC-49/U (-S) KINSEKI LTD.
10.00 12.00 16.00
0 (i) 0 470k (ii)
P3
32.768kHz
Selection Guide Option item Package ROM capacitance Reset pin pull-up resistor Input circuit format1 Mask product 100-pin plastic QFP 52K bytes /60K bytes Existent /Non-existent CMOS Schmitt /TTL Schmitt CXP878P60Q-1100-pin plastic QFP PROM 60K bytes Existent TTL Schmitt
1 Pins PG4/SYNC0, PG5/SYNC1 only.
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CXP878P60
Characteristics Curve
IDD vs. VDD
(fc = 16MHz, Ta = 25C, Typical)
IDD vs. fc
(VDD = 5.0V, Ta = 25C, Typical)
1/2 dividing mode 1/4 dividing mode 10 1/16 dividing mode Sleep mode
40
30
IDD - Supply current [mA]
32kHz mode (instruction)
IDD - Supply current [mA]
1
1/2 dividing mode 20
0.1
32kHz Sleep mode
0.01 (10A)
1/4 dividing mode 10 1/16 dividing mode Sleep mode 0
2.5
3.0
3.5 4.5 4.0 5.0 5.5 VDD - Supply voltage [V]
6.0
0
5 10 fc - System clock [MHz]
15
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CXP878P60
Package Outline
Unit: mm
100PIN QFP (PLASTIC)
+ 0.1 0.15 - 0.05
23.9 0.4 + 0.4 20.0 - 0.1
+ 0.4 14.0 - 0.01 17.9 0.4
15.8 0.4
A
0.65 0.12 M
+ 0.35 2.75 - 0.15
0.15
0 to 15 DETAIL A
0.8 0.2
(16.3)
PACKAGE STRUCTURE
PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE QFP-100P-L01 QFP100-P-1420-A LEAD TREATMENT LEAD MATERIAL PACKAGE WEIGHT EPOXY RESIN SOLDER PLATING COPPER / 42 ALLOY 1.4g
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